WDC 65816/65802 microcontroller architecture

The W65C816S (also 65C816 or 65816) is a 16 bit microprocessor (MPU) developed by the Western Design Center (WDC). The W65C816S is an enhanced version of the WDC 65C02 8 bit MPU, itself aCMOS enhancement of the venerable MOS Technology 6502 NMOS MPU. The 65 in the part's designation comes from its 65C02 compatibility mode, and the 816 signifies that the MPU has selectable 8– and 16–bitregister sizes.

In addition to the availability of 16 bit registers, the W65C816S features extended memory addressing to 24 bits, supporting up to 16 megabytes of random access memory, an enhanced instruction set, and a 16 bitstack pointer, as well as several new electrical signals for improved system hardware management.

At reset, the W65C816S starts in "emulation mode," meaning it essentially behaves as a 65C02. Following reset, the W65C816S may be switched to "native mode" with a two instruction sequence, causing it to enable all enhanced features, yet still maintain a substantial degree of backward compatibility with most 65C02 software. However, unlike the PDIP40 version of the 65C02, which is a pin-compatible replacement for its NMOS ancestor, the PDIP40 W65C816S (illustrated above) is not.

FEATURES OF WDC 95816/65802

• Fully static CMOS design for low power consumption (300 µA at one MHz) and increased noise immunity.
• Wide operating voltage range: 1.8 V ± 5%, 2.5 V ± 5%, 3.0 V ± 5%, 3.3 V ± 10%, 5.0 V ± 5% for use with varying voltage peripherals.
• Wide operating frequency range.
• Emulation mode allows complete software compatibility with the 65C02, excepting undocumented opcodes.
• 24-bit memory addressing provides access to 16 MB of memory space.
• 16-bit ALU, accumulator, stack pointer and index registers.
• Valid Data Address (VDA) and Valid Program Address (VPA) outputs for dual cache and cycle steal DMA implementation.
• Vector Pull (VPB) output to indicate when an interrupt vector is being addressed.
• Abort (ABORTB) input and associated vector supports processor repairs of bus error conditions, such as memory access violations.
• Separate program and data bank registers allow program segmentation or 16 MB linear addressing (data only).
• Direct register and stack relative addressing provides capability for reentrant, recursive and re-locatable programming.
• 24 addressing modes—13 original 6502 modes with 92 instructions using 256 op codes, including most new opcodes implemented in the 65C02.
• Wait-for-Interrupt (WAI) and Stop-the-Clock (STP) instructions further reduce power consumption, decrease interrupt latency and allows synchronization with external events.
• Co-Processor (COP) instruction with associated vector supports co-processor configurations, e.g., floating point processors
• Reserved "escape" opcode (WDM) for use in future designs (e.g., the yet-to-be-release Terbium 32 bit MPU).
• Block-move instructions, allowing rapid copying of data structures from one area of RAM to another with minimal code.