W65C02S microcontroller

The W65C02S is Western Design Center's version of the 65C02 microprocessor. The "S" designation indicates that the part has a fully staticcore which allows the primary clock to be slowed down indefinitely or fully stopped in either the high or low state.

The W65C02S is a low-power general-purpose 8-bit microprocessor (8-bit registers and data bus) with a 16-bit program counter and address bus. The variable length instruction set and manually optimized core size are intended to make the W65C02S be well suited for low powersystem-on-chip (SoC) designs.

WDC makes a Verilog hardware description model available for designing the 65C02 core into ASICs and FPGAs. As is common in the semiconductor industry, the company also provides a development system, which includes a developer board, an in-circuit emulator (ICE) and a software development system.

General logic features

• 8-bit data bus
• 16-bit address bus (providing an address space of 64K bytes)
• 8-bit arithmetic logic unit (ALU)
• 
  
  8-bit processor registers:
  
  • accumulator
  • stack pointer
  • index registers
  • status register
  
  
• 16-bit program counter
• 69 instructions, implemented by 212 operation codes
• 16 addressing modes, including zero page addressing

Logic specifics

• Vector Pull (VPB) output indicates when interrupt vectors are being addressed
• WAit-for-Interrupt (WAI) and SToP (STP) instructions reduce power consumption, decrease interrupt latency and enable synchronization with external events

Electrical features

• Supply voltage specified at 1.71V to 5.25V
• Current consumption (core) of 0.15 and 1.5 mA per MHz at 1.89V and 5.25V respectively
• Variable length instruction set, enabling code size optimization over fixed length instruction set processors, results in power savings
• Fully static circuitry allows stopping the clock to conserve power

The WDC 65C02 can run at any supply voltage (VDD) between 1.8 and 5 volts (±5%). There are not different chips for different logic supply voltages. The data sheet shows graphs of how various parameters (e.g. IDD, Fmax) change with VDD, and tables showing their values at commonly used VDD values (1.8, 2.5, 3.0, 3.3, 5.0 V ±5%).

The WDC6502 data sheet table 6.3 shows AC characteristics at 5V/14MHz, 3.3V/8MHz, 3V/8MHz, 2.5V/4MHz, and 1.8V/2MHz. This may be left over from an earlier data sheet, because the graph in figure 6.2 indicates that typical devices run over 18 MHz at 4V, and 6MHz at 1.8V.

The -14 suffix should not be taken as a 14 MHz hard limit. The WDC6502 may well run at convenient clocks such as 13.5 MHz (digital SDTV luma sampling rate), 14.31818.. MHz (NTSC colour carrier x 4), 14.75 MHz (PAL square pixels), 14.7456 (baud rate crystal), 16 MHz and so on. However, the minimum VDD value rises accordingly.

Bill Mensch pointed out that Fmax depends on off-chip factors such as the capacitive load on the pins. Minimising load by using short signal tracks and fewest devices helps raise Fmax. The PLCC package has less pin-to-pin capacitance than the DIP40 package.