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EMI 2nd internal exam important question and answers for jntu ECE 4-1

Oscilloscope cro's

An oscilloscope is a test instrument which allows you to look at the 'shape' of electrical signals by displaying a graph of voltage against time on its screen. It is like a voltmeter with the valuable extra function of showing how the voltage varies with time. A graticule with a 1cm grid enables you to take measurements of voltage and time from the screen.
The graph, usually called the trace, is drawn by a beam of electrons striking the phosphor coating of the screen making it emit light, usually green or blue. This is similar to the way a television picture is produced.
Oscilloscopes contain a vacuum tube with a cathode (negative electrode) at one end to emit electrons and an anode (positive electrode) to accelerate them so they move rapidly down the tube to thescreen. This arrangement is called an electron gun. The tube also contains electrodes to deflect the electron beam up/down and left/right.
The electrons are called cathode rays because they are emitted by the cathode and this gives the oscilloscope its full name of cathode ray oscilloscope or CRO.
A dual trace oscilloscope can display two traces on the screen, allowing you to easily compare the input and output of an amplifier for example. It is well worth paying the modest extra cost to have this facility.
Precautions:-
• An oscilloscope should be handled gently to protect its fragile (and expensive) vacuum tube.
• Oscilloscopes use high voltages to create the electron beam and these remain for some time after switching off - for your own safety do not attempt to examine the inside of an oscilloscope!
Setting up an oscilloscope:-
Oscilloscopes are complex instruments with many controls and they require some care to set up and use successfully. It is quite easy to 'lose'the trace off the screen if controls are set wrongly!
There is some variation in the arrangement and labeling of the many controls so the following instructions may need to be adapted for your instrument.
1. Switch on the oscilloscope to warm up (it takes a minute or two).
2. Do not connect the input lead at this stage.
3. Set the AC/GND/DC switch (by the Y INPUT) to DC.
4. Set the SWP/X-Y switch to SWP (sweep).
5. Set Trigger Level to AUTO.
6. Set Trigger Source to INT (internal, the y input).
7. Set the Y AMPLIFIER to 5V/cm (a moderate value).
8. Set the TIMEBASE to 10ms/cm (a moderate speed).
9. Turn the timebase VARIABLE control to 1 or CAL.
10. Adjust Y SHIFT (up/down) and X SHIFT (left/right) to give a trace across the middle of the screen, like the picture.
11. Adjust INTENSITY (brightness) and FOCUS to give a bright, sharp trace.
12. The oscilloscope is now ready to use!
Connecting the input lead is described in the next section.

Connecting an oscilloscope:-

The Y INPUT lead to an oscilloscope should be a co-axial lead and the diagram shows its construction. The central wire carries the signal and the screen is connected to earth (0V) to shield the signal from electrical interference (usually called noise).

Most oscilloscopes have a BNC socket for the y input and the lead is connected with a push and twist action, to disconnect you need to twist and pull. Oscilloscopes used in schools may have red and black 4mm sockets so that ordinary, unscreened, 4mm plug leads can be used if necessary.
Professionals use a specially designed lead and probes kit for best results with high frequency signals and when testing high resistance circuits, but this is not essential for simpler work at audio frequencies (up to 20kHz).
An oscilloscope is connected like a voltmeter but you must be aware that the screen (black) connection of the input lead is connected to mains earth at the oscilloscope! This means it must be connected to earth or 0V on the circuit being tested.
Obtaining a clear and stable trace:-
Once you have connected the oscilloscope to the circuit you wish to test you will need to adjust the controls to obtain a clear and stable trace on the screen:
• The Y AMPLIFIER (VOLTS/CM) control determines the height of the trace. Choose a setting so the trace occupies at least half the screen height, but does not disappear off the screen.
• The TIMEBASE (TIME/CM) control determines the rate at which the dot sweeps across the screen. Choose a setting so the trace shows at least one cycle of the signal across the screen.
Note that a steady DC input signal gives a horizontal line trace for which the timebase setting is not critical.
• The TRIGGER control is usually best left set to AUTO.
If you are using an oscilloscope for the first time it is best to start with an easy signal such as the output from an AC power pack set to about 4V.
Measuring voltage and time period
The trace on an oscilloscope screen is a graph of voltage against time. The shape of this graph is determined by the nature of the input signal.
In addition to the properties labelled on the graph, there is frequency which is the number of cycles per second.
The diagram shows a sine wave but these properties apply to any signal with a constant shape.

• Amplitude is the maximum voltage reached by the signal.
It is measured in volts, V.
• Peak voltage is another name for amplitude.
• Peak-peak voltage is twice the peak voltage (amplitude). When reading an oscilloscope trace it is usual to measure peak-peak voltage.
• Time period is the time taken for the signal to complete one cycle.
It is measured in seconds (s), but time periods tend to be short so milliseconds (ms) and microseconds (µs) are often used. 1ms = 0.001s and 1µs = 0.000001s.
• Frequency is the number of cycles per second.
It is measured in hertz (Hz), but frequencies tend to be high so kilohertz (kHz) and megahertz (MHz) are often used. 1kHz = 1000Hz and 1MHz = 1000000Hz.

Voltage:-

Voltage is shown on the vertical y-axis and the scale is determined by the Y AMPLIFIER (VOLTS/CM) control. Usually peak-peak voltage is measured because it can be read correctly even if the position of 0V is not known. The amplitude is half the peak-peak voltage.
If you wish to read the amplitude voltage directly you must check the position of 0V (normally halfway up the screen): move the AC/GND/DC switch to GND (0V) and use Y-SHIFT (up/down) to adjust the position of the trace if necessary, switch back to DC afterwards so you can see the signal again.
Voltage = distance in cm × volts/cm
Example: peak-peak voltage = 4.2cm × 2V/cm = 8.4V
amplitude (peak voltage) = ½ × peak-peak voltage = 4.2V
Time period
Time is shown on the horizontal x-axis and the scale is determined by the TIMEBASE (TIME/CM) control. The time period (often just called period) is the time for one cycle ofthe signal. The frequency is the number of cyles per second, frequency = 1/time period
Ensure that the variable timebase control is set to 1 or CAL (calibrated) before attempting to take a time reading.
Time = distance in cm × time/cm
Example: time period = 4.0cm × 5ms/cm = 20ms
and frequency = 1/time period = 1/20ms = 50Hz
Timebase (time/cm) and trigger controls:-
The oscilloscope sweeps the electron beam across the screen from left to right at a steady speed set by the TIMEBASE control.

Each setting is labelled with the time the dot takes to move 1cm, effectively it is setting the scale on the x-axis.The timebase control may be labelled TIME/CM.

At slow timebase settings (such as 50ms/cm) you can see a dot moving across the screen but at faster settings (such as 1ms/cm) the dot is moving so fast that it appears to be a line.
The VARIABLE timebase control can be turned to make a fine adjustment to the speed, but it must be left at the position labelled 1 or CAL (calibrated) if you wish to take time readings from the trace drawn on the screen.

The TRIGGER controls are used to maintain a steady trace on the screen. If they are set wrongly you may see a trace drifting sideways, a confusing 'scribble' on the screen, or no trace at all! The trigger maintains a steady trace by starting the dot sweeping across the screen when the input signal reaches the same point in its cycle each time.

For straightforward use it is best to leave the trigger level set to AUTO, but if you have difficulty obtaining a steady trace try adjusting this control to set the level manually.

Y amplifier (volts/cm) control:-

The oscilloscope moves the trace up and down in proportion to the voltage at the Y INPUT and the setting of the Y AMPLIFIER control. This control sets the voltage represented by each centimetre (cm) on the the screen, effectively it is setting the scale on the y-axis. Positive voltages make the trace move up, negative voltages make it move down.
The y amplifier control may be labelled Y-GAIN or VOLTS/CM.
The input voltage moving the dot up and down at the same time as the dot is swept across the screen means that the trace on the screen is a graph of voltage (y-axis) against time (x-axis) for the input signal.

The AC/GND/DC switch:-

The normal setting for this switch is DC for all signals, including AC!
Switching to GND (ground) connects the y input to 0V and allows you to quickly check the position of 0V on the screen (normally halfway up). There is no need to disconnect the input lead while you do this because it is disconnected internally.
Switching to AC inserts a capacitor in series with the input to block out any DC signal present and pass only AC signals. This is used to examine signals showing a small variation around one constant value, such as the ripple on the output of a smooth DC supply. Reducing the VOLTS/CM to see more detail of the ripple would normally take the trace off the screen! The AC setting removes the constant (DC) part of the signal, allowing you to view just the varying (AC) part which can now be examined more closely by reducing the VOLTS/CM. This is shown in the diagrams below:

Displaying a ripple signal using the AC switch

what ia a Function generator

A Function Generator or sometimes called a Waveform Generator is a device or circuit that produces a variety of different waveforms at a desired frequency. It can generate Sine waves, Square waves, Triangular and Sawtooth waveforms as well as other types of output waveforms. There are many "off-the-shelf" waveform generator IC's available and all can be incorporated into a circuit to produce the different periodic waveforms.
One such device is the 8038 a precision waveform generator IC capable of producing sine, square and triangular output waveforms, with a minimum number of external components or adjustments. Its operating frequency range can be selected over eight decades of frequency, from 0.001Hz to 300kHz, by the correct choice of the external R-C components.

The frequency of oscillation is highly stable over a wide range of temperature and supply voltage changes and frequencies as high as 1MHz is possible. Each of the three basic waveform outputs, sine, triangle and square are simultaneously available from independent output terminals. The frequency range of the 8038 is voltage controllable but not a linear function. The triangle symmetry and hence the sine wave distortion are adjustable.

Monostable Multivibrators

Monostable Multivibrators
Multivibrators are the most commonly used of all the square wave generators and which themselves belong to a family of oscillators commonly called "Relaxation Oscillators". Generally speaking, discrete multivibrators consist of a two transistors cross coupled amplifier circuit with a Resistor and Capacitor (RC) network connected across them to produce the feedback tank circuit. Multivibrators have two different electrical states, an output "HIGH" state and an output "LOW" state. One such type of a two state pulse generator configuration are called Monostable Multivibrators.
Monostable Multivibrators have only ONE stable state (hence there name: "Mono"), and they deliver a single output pulse when it is triggered externally only returning back to its first original and stable state after a period of time determined by the time constant of the RC coupled circuit. Monostable Multivibrators or "One-Shot Multivibrators" as they are sometimes called are used to generate a single output pulse of a specified width, either "High" or "Low" when a suitable external trigger signal or pulse T is applied. This trigger signal initiates a timing cycle which causes the output of the monostable to change its state at the start of the timing cycle and remains in this second state, which is determined by the time constant of the Capacitor, C and the Resistor, R until it resets or returns itself back to its original (stable) state. It will remain in this stable state indefinitely until another input pulse or signal is received. Then, Monostable Multivibrators have only ONE stable state and go through a full cycle in response to a single triggering input pulse.
Monostable Multivibrator Circuit The basic Collector-coupled Monostable Multivibrator circuit and its associated waveforms are shown above. When power is firstly applied, the base of transistor TR2 is connected to Vcc via the biasingresistor, R2 thereby turning the transistor "fully-ON" and into saturation and at the same time turning TR1 "OFF" in the process. This then represents the circuits "Stable State" with zero output. The current flowing into the saturated Base terminal of TR2 will therefore be equal to Ib = (Vcc - 0.6)/R2.
If a trigger pulse is now applied at the input, the fast rising edge of the pulse will pass straight through capacitor, C1 to the Base of transistor, TR1 turning it "ON". The Collector of TR1 which was previously at Vcc drops quickly to below zero volts effectively givingcapacitor C2 a reverse charge of -0.6v across its plates. This result in transistor TR2 now having a Base voltage of -0.6v holding the transistor fully "OFF" at point VbTR2. This then represents the circuits second state, the "Unstable State" with an output voltage equal to Vcc.
Capacitor, C2 begins to discharge this -0.6v through resistor R2, attempting to charge up to the supply voltage Vcc. This negative voltage at the Base of transistor TR2 begins to decrease gradually at a rate determined bythe time constant of the C2-R2 combination. As the Base voltage of TR2 increases back up to Vcc, the transistor begins to conduct and doing so turns "OFF" again transistor TR1 which results in the monostable multivibrator automatically returning back to its original stable state awaiting a second trigger pulse to restart the process once again.
Monostable Multivibrators can produce a very short pulse or a much longer rectangular shaped waveform whose leading edge rises in time with the externally applied trigger pulse and whose trailing edge is dependent upon the RC time constant of the feedback components used. This RC time constant may be varied with time toproduce a series of pulses which have a controlled fixed time delay in relation to the original trigger pulse as shown below.
Monostable Multivibrator Waveforms
The time constant of Monostable Multivibrators can be changed by varying the values of the Capacitor, C2 the Resistor, R2 or both. Monostable Multivibrators are generally used to increase the width of a pulse or to produce a time delay within a circuit as the frequency of the output signal is always the same as that for the trigger pulse input, the only difference is the pulse width.
TTL/CMOS Monostable Multivibrators
As well as producing Monostable Multivibrators from individual discrete components such as transistors, we can also construct monostable circuits using commonly available integrated circuits. The following circuit shows how a basic monostable multivibrator circuit can be constructed using just two 2-input Logic "NOR" Gates.
NOR Gate Monostable

Suppose initially that the trigger input is Low at a logic level "0" so that the output from the NOR gate U1 is High at logic level "1", (NOR Gate principals). Theresistor, R is connected to the supply voltage so is equal to logic level "1", which means that the capacitor , C has the same charge on both plates and junction V1 is equal to this voltage, so the output from the second NOR gate U2 will be Low at logic level "0". This then represents the circuits "Stable State" with zero output.
When a trigger pulse is applied to the input at time to, the output of U1 goes Low taking with it capacitor C. As both plates of the capacitor are at logic level "0" so to is the input to the second NOR gate, U2 resulting in an output equal to logic level "1". This then represents the circuitssecond state, the "Unstable State" with an output voltage equal to Vcc.
The second NOR gate, U2 will maintain this second unstable state until the capacitor now charging up through resistor, R reaches the input threshold voltage of U2 causing it to change state, automatically returning itself back to its original stable state and awaiting a second trigger pulse to restart the timing process once again.
NOR Gate Monostable Waveforms
This then gives us an equation for the time period of the circuit as:
tow =0.7RC

Where, R is in Ω's and C in Farads.
We can also make monostable pulse generators using special IC's and there are already integrated circuits dedicated to this such as the 74LS121 standard one shot monostable multivibrator or the 74LS123 re-triggerable monostable multivibrator which canproduce output pulse widths from as low as 40 nanoseconds up to 28 seconds by using only two external RC timing components with the pulse width given as: T = 0.7RC in seconds.
Monostable Multivibrators Summary
Then to summarize, the Monostable Multivibrator circuit has only ONE stable state. When triggered by a short external trigger pulse it changes state and remains in thissecond state for an amount of time determined by the preset time period of the RC feedback components used. One this time period has passed the monostable automatically returns itself back to its original low state awaiting a second trigger pulse. Monostable Multivibrators can therefore be considered as triggered pulse generators and are generally used toproduce a time delay within a circuit as the frequency of the output signal is the same as that for the trigger pulse input the only difference being the pulse width. One main disadvantage of Monostable Multivibrators is thatthe time between the application of the next trigger pulse has to be greater than the preset RC time constant of the circuit to allow thecapacitor time to charge and discharge.

Darlington Transistors

Darlington Transistors
Sometimes the DC current gain of the bipolar transistor is too low to directly switch the load current or voltage, so multiple switching transistors are used. Here, one small input transistor is used to switch "ON" or "OFF" a much larger current handling output transistor. To maximise the signal gain the two transistors are connected in a "Complementary Gain Compounding Configuration" or what is generally called a "Darlington Configuration" where the amplification factor is the product of the two individual transistors.
Darlington Transistors simply contain two individual bipolar NPN or PNP type transistors connected together so that the current gain of the first transistor is multiplied with that of the current gain of the second transistor to produce a device which acts like a single transistor with a very high current gain. The overall current gain Beta (β) or Hfe value of a Darlington device is the product of the two individual gains of the transistors and is given as:
So Darlington Transistors with very high β values and high Collector currents are possible compared to a single transistor. An example of the two basic types of Darlington transistor are given below.
Darlington Transistor Configurations

The above NPN Darlington transistor configuration shows the Collectors of the two transistors connected together with the Emitter of the first transistor connected to the Base of the second transistor therefore, the Emitter current of the first transistor becomes the Base current of the second transistor. The first or "input" transistor receives an input signal, amplifies it and uses it to drive the second or "output" transistors which amplifies it again resulting in a very high current gain. As well as its high increased current and voltage switching capabilities, another advantage of a Darlington transistor is in its high switching speeds making them ideal for use in Inverter circuits and DC motor or stepper motor control applications.
One difference to consider when using Darlington transistors over the conventional single bipolar transistor type is that the Base-Emitter input voltage Vbe needs to be higher at approx 1.4v for silicon devices, due to the series connection of the two PN junctions.
Then to summarise when using a Transistor as a Switch.

· Transistor switches can be used to switch and control lamps, relays or even motors.
· When using bipolar transistors as switches they must be fully "OFF" or fully "ON".
· Transistors that are fully "ON" are said to be in their Saturation region.
· Transistors that are fully "OFF" are said to be in their Cut-off region.
· In a transistor switch a small Base current controls a much larger Collector current.
· When using transistors to switch inductive relay loads a "Flywheel Diode" is required.
· When large currents or voltages need to be controlled, Darlington Transistors are used

Transistor as a switch

The Transistor as a Switch
When used as an AC signal amplifier, the transistors Base biasing voltage is applied so that it operates within its "Active" region and the linear part of the output characteristics curves are used. However, both the NPN & PNP type bipolar transistors can be made to operate as an "ON/OFF" type solid state switch for controlling high power devices such as motors, solenoids or lamps. If the circuit uses the Transistor as a Switch, then the biasing is arranged to operate in the output characteristics curves seen previously in the areas known as the "Saturation" and "Cut-off" regions as shown below.

Transistor Curves

The pink shaded area at the bottom represents the "Cut-off" region. Here the operating conditions of the transistor are zero input base current (Ib), zero output collector current (Ic) and maximum collector voltage (Vce) which results in a large depletion layer and no current flows through the device. The transistor is switched "Fully-OFF". The lighter blue area to the left represents the "Saturation" region. Here the transistor will be biased so that the maximum amount of base current is applied, resulting in maximum collector current flow and minimum collector emitter voltage which results in the depletion layer being as small as possible and maximum current flows through the device. The transistor is switched "Fully-ON". Then we can summarize this as:

1. Cut-off Region - Both junctions are Reverse-biased, Base current is zero or very small resulting in zero Collector current flowing, the device is switched fully "OFF".
2. Saturation Region - Both junctions are Forward-biased, Base current is high enough to give a Collector-Emitter voltage of 0v resulting in maximum Collector current flowing, the device is switched fully "ON".

An example of an NPN Transistor as a switch being used to operate a relay is given below. With inductive loads such as relays or solenoids a flywheel diode is placed across the load to dissipate the back EMF generated by the inductive load when the transistor switches "OFF" and so protect the transistor from damage. If the load is of a very high current or voltage nature, such as motors, heaters etc, then the load current can be controlled via a suitable relay as shown.

Transistor Switching Circuit

The circuit resembles that of the Common Emitter circuit we looked at in the previous tutorials. The difference this time is that to operate the transistor as a switch the transistor needs to be turned either fully "OFF" (Cut-off) or fully "ON" (Saturated). An ideal transistor switch would have an infinite resistance when turned "OFF" resulting in zero current flow and zero resistance when turned "ON", resulting in maximum current flow. In practice when turned "OFF", small leakage currents flow through the transistor and when fully "ON" the device has a low resistance value causing a small saturation voltage (Vce) across it. In both the Cut-off and Saturation regions the power dissipated by the transistor is at its minimum.To make the Base current flow, the Base input terminal must be made more positive than the Emitter by increasing it above the 0.7 volts needed for a silicon device. By varying the Base-Emitter voltage Vbe, the Base current is altered and which in turn controls the amount of Collector current flowing through the transistor as previously discussed. When maximum Collector current flows the transistor is said to be Saturated. The value of the Base resistor determines how much input voltage is required and corresponding Base current to switch the transistor fully "ON".

What are Logic gates

A logic gate is an elementary building block of a digital circuits . Most logic gates have two inputs and one output. At any given moment, every terminal is in one of the two binary conditions low (0) or high (1), represented by different voltage levels. The logic state of a terminal can, and generally does, change often, as the circuit processes data. In most logic gates, the low state is approximately zero volts (0 V), while the high state is approximately five volts positive (+5 V). There are seven basic logic gates: AND, OR, XOR, NOT, NAND, NOR, and XNOR. The AND gate is so named because, if 0 is called "false" and 1 is called "true," the gate acts in the same way as the logical "and" operator. The following illustration and table show the circuit symbol and logic combinations for an AND gate. (In the symbol, the input terminals are at left and the output terminal is at right.) The output is "true" when both inputs are "true." Otherwise, the output is "false." AND gate

Input 1	Input 2	Output
0	0	0
0	1	0
1	0	0
1	1	1

The OR gate gets its name from the fact that it behaves after the fashion of the logical inclusive "or." The output is "true" if either or both of the inputs are "true." If both inputs are "false," then the output is "false."

OR gate

Input 1	Input 2	Output
0	0	0
0	1	1
1	0	1
1	1	1

The XOR ( exclusive-OR ) gate acts in the same way as the logical "either/or." The output is "true" if either, but not both, of the inputs are "true." The output is "false" if both inputs are "false" or if both inputs are "true." Another way of looking at this circuit is to observe that the output is 1 if the inputs are different, but 0 if the inputs are the same.

XOR gate

Input 1	Input 2	Output
0	0	0
0	1	1
1	0	1
1	1	0

A logical inverter , sometimes called a NOT gate to differentiate it from other types of electronic inverter devices, has only one input. It reverses the logic state.

Inverter or NOT gate

Input	Output
1	0
0	1

The NAND gate operates as an AND gate followed by a NOT gate. It acts in the manner of the logical operation "and" followed by negation. The output is "false" if both inputs are "true." Otherwise, the output is "true."

NAND gate

Input 1	Input 2	Output
0	0	1
0	1	1
1	0	1
1	1	0

The NOR gate is a combination OR gate followed by an inverter. Its output is "true" if both inputs are "false." Otherwise, the output is "false."

NOR gate

Input 1	Input 2	Output
0	0	1
0	1	0
1	0	0
1	1	0

The XNOR (exclusive-NOR) gate is a combination XOR gate followedby an inverter. Its output is "true" if the inputs are the same, and"false" if the inputs are different.

XNOR gate

Input 1	Input 2	Output
0	0	1
0	1	0
1	0	0
1	1	1

Using combinations of logic gates, complex operations can be performed. In theory, there is no limit to the number of gates that can be arrayed together in a single device. But in practice, there is a limit to the number of gates that can be packed into a given physical space. Arrays of logic gates are found in digital integrated circuits (ICs). As IC technology advances, the required physical volume for each individual logic gate decreases and digital devices of the same or smaller size become capable of performing ever-more-complicated operations at ever-increasing speeds.

Positive feedback

As we've seen, negative feedback is an incredibly useful principle when applied to operational amplifiers. It is what allows us to create all these practical circuits, being able to precisely set gains, rates, and other significant parameters with just a few changes of resistor values. Negative feedback makes all these circuits stable and self-correcting.

The basic principle of negative feedback is that the output tends to drive in a direction that creates a condition of equilibrium (balance). In an op-amp circuit with no feedback, there is no corrective mechanism, and the output voltage will saturate with the tiniest amount of differential voltage applied between the inputs. The result is a comparator:

With negative feedback (the output voltage "fed back" somehow to the inverting input), the circuit tends to prevent itself from driving the output to full saturation. Rather, the output voltage drives only as high or as low as needed to balance the two inputs' voltages:

Whether the output is directly fed back to the inverting (-) input or coupled through a set of components, the effect is the same: the extremely high differential voltage gain of the op-amp will be "tamed" and the circuit will respond according to the dictates of the feedback "loop" connecting output to inverting input.

Another type of feedback, namely positive feedback, also finds application in op-amp circuits. Unlike negative feedback, where the output voltage is "fed back" to the inverting (-) input, with positive feedback the output voltage is somehow routed back to the noninverting (+) input. In its simplest form, we could connect a straight piece of wire from output to noninverting input and see what happens:

The inverting input remains disconnected from the feedback loop, and is free to receive an external voltage. Let's see what happens if we ground the inverting input:

With the inverting input grounded (maintained at zero volts), the output voltage will be dictated by the magnitude and polarity of the voltage at the noninverting input. If that voltage happens to be positive, the op-amp will drive its output positive as well, feeding that positive voltage back to the noninverting input, which will result in full positive output saturation. On the other hand, if the voltage on the noninverting input happens to start out negative, the op-amp's output will drive in the negative direction, feeding back to the noninverting input and resulting in full negative saturation.

What we have here is a circuit whose output is bistable: stable in one of two states (saturated positive or saturated negative). Once it has reached one of those saturated states, it will tend to remain in that state, unchanging. What is necessary to get it to switch states is a voltage placed upon the inverting (-) input of the same polarity, but of a slightly greater magnitude. For example, if our circuit is saturated at an output voltage of +12 volts, it will take an input voltage at the inverting input of at least +12 volts to get the output to change. When it changes, it will saturate fully negative.

So, an op-amp with positive feedback tends to stay in whatever output state its already in. It "latches" between one of two states, saturated positive or saturated negative. Technically, this is known as hysteresis.

Hysteresis can be a useful property for a comparator circuit to have. As we've seen before, comparators can be used to produce a square wave from any sort of ramping waveform (sine wave, triangle wave, sawtooth wave, etc.) input. If the incoming AC waveform is noise-free (that is, a "pure" waveform), a simple comparator will work just fine.

However, if there exist any anomalies in the waveform such as harmonics or "spikes" which cause the voltage to rise and fall significantly within the timespan of a single cycle, a comparator's output might switch states unexpectedly:

Any time there is a transition through the reference voltage level, no matter how tiny that transition may be, the output of the comparator will switch states, producing a square wave with "glitches."

If we add a little positive feedback to the comparator circuit, we will introduce hysteresis into the output. This hysteresis will cause the output to remain in its current state unless the AC input voltage undergoes a major change in magnitude.

What this feedback resistor creates is a dual-reference for the comparator circuit. The voltage applied to the noninverting (+) input as a reference which to compare with the incoming AC voltage changes depending on the value of the op-amp's output voltage. When the op-amp output is saturated positive, the reference voltage at the noninverting input will be more positive than before. Conversely, when the op-amp output is saturated negative, the reference voltage at the noninverting input will be more negative than before. The result is easier to understand on a graph:

When the op-amp output is saturated positive, the upper reference voltage is in effect, and the output won't drop to a negative saturation level unless the AC input rises above that upper reference level. Conversely, when the op-amp output is saturated negative, the lower reference voltage is in effect, and the output won't rise to a positive saturation level unless the AC input drops below that lower reference level. The result is a clean square-wave output again, despite significant amounts of distortion in the AC input signal. In order for a "glitch" to cause the comparator to switch from one state to another, it would have to be at least as big (tall) as the difference between the upper and lower reference voltage levels, and at the right point in time to cross both those levels.

Another application of positive feedback in op-amp circuits is in the construction of oscillator circuits. An oscillator is a device that produces an alternating (AC), or at least pulsing, output voltage. Technically, it is known as an astable device: having no stable output state (no equilibrium whatsoever). Oscillators are very useful devices, and they are easily made with just an op-amp and a few external components.

When the output is saturated positive, the V_ref will be positive, and the capacitor will charge up in a positive direction. When V_ramp exceeds V_ref by the tiniest margin, the output will saturate negative, and the capacitor will charge in the opposite direction (polarity). Oscillation occurs because the positive feedback is instantaneous and the negative feedback is delayed (by means of an RC time constant). The frequency of this oscillator may be adjusted by varying the size of any component.

• REVIEW:
• Negative feedback creates a condition of equilibrium (balance). Positive feedback creates a condition of hysteresis (the tendency to "latch" in one of two extreme states).
• An oscillator is a device producing an alternating or pulsing output voltage.

CMOS GATE CIRCUITARY

Up until this point, our analysis of transistor logic circuits has been limited to the TTL design paradigm, whereby bipolar transistors are used, and the general strategy of floating inputs being equivalent to "high" (connected to V_cc) inputs -- and correspondingly, the allowance of "open-collector" output stages -- is maintained. This, however, is not the only way we can build logic gates.

Field-effect transistors, particularly the insulated-gate variety, may be used in the design of gate circuits. Being voltage-controlled rather than current-controlled devices, IGFETs tend to allow very simple circuit designs. Take for instance, the following inverter circuit built using P- and N-channel IGFETs:

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Notice the "V_dd" label on the positive power supply terminal. This label follows the same convention as "V_cc" in TTL circuits: it stands for the constant voltage applied to the drain of a field effect transistor, in reference to ground.

Let's connect this gate circuit to a power source and input switch, and examine its operation. Please note that these IGFET transistors are E-type (Enhancement-mode), and so are normally-off devices. It takes an applied voltage between gate and drain (actually, between gate and substrate) of the correct polarity to bias them on.

The upper transistor is a P-channel IGFET. When the channel (substrate) is made more positive than the gate (gate negative in reference to the substrate), the channel is enhanced and current is allowed between source and drain. So, in the above illustration, the top transistor is turned on.

The lower transistor, having zero voltage between gate and substrate (source), is in its normal mode: off. Thus, the action of these two transistors are such that the output terminal of the gate circuit has a solid connection to V_dd and a very high resistance connection to ground. This makes the output "high" (1) for the "low" (0) state of the input.

Next, we'll move the input switch to its other position and see what happens:

Now the lower transistor (N-channel) is saturated because it has sufficient voltage of the correct polarity applied between gate and substrate (channel) to turn it on (positive on gate, negative on the channel). The upper transistor, having zero voltage applied between its gate and substrate, is in its normal mode: off. Thus, the output of this gate circuit is now "low" (0). Clearly, this circuit exhibits the behavior of an inverter, or NOT gate.

Using field-effect transistors instead of bipolar transistors has greatly simplified the design of the inverter gate. Note that the output of this gate never floats as is the case with the simplest TTL circuit: it has a natural "totem-pole" configuration, capable of both sourcing and sinking load current. Key to this gate circuit's elegant design is the complementary use of both P- and N-channel IGFETs. Since IGFETs are more commonly known as MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistor), and this circuit uses both P- and N-channel transistors together, the general classification given to gate circuits like this one isCMOS: Complementary Metal Oxide Semiconductor.

CMOS circuits aren't plagued by the inherent nonlinearities of the field-effect transistors, because as digital circuits their transistors always operate in either the saturated or cutoff modes and never in the activemode. Their inputs are, however, sensitive to high voltages generated by electrostatic (static electricity) sources, and may even be activated into "high" (1) or "low" (0) states by spurious voltage sources if left floating. For this reason, it is inadvisable to allow a CMOS logic gate input to float under any circumstances. Please note that this is very different from the behavior of a TTL gate where a floating input was safely interpreted as a "high" (1) logic level.

This may cause a problem if the input to a CMOS logic gate is driven by a single-throw switch, where one state has the input solidly connected to either V_dd or ground and the other state has the input floating (not connected to anything):

Also, this problem arises if a CMOS gate input is being driven by an open-collector TTL gate. Because such a TTL gate's output floats when it goes "high" (1), the CMOS gate input will be left in an uncertain state:

Fortunately, there is an easy solution to this dilemma, one that is used frequently in CMOS logic circuitry. Whenever a single-throw switch (or any other sort of gate output incapable of both sourcing and sinking current) is being used to drive a CMOS input, a resistor connected to either V_dd or ground may be used to provide a stable logic level for the state in which the driving device's output is floating. This resistor's value is not critical: 10 kΩ is usually sufficient. When used to provide a "high" (1) logic level in the event of a floating signal source, this resistor is known as a pullup resistor:

When such a resistor is used to provide a "low" (0) logic level in the event of a floating signal source, it is known as a pulldown resistor. Again, the value for a pulldown resistor is not critical:

Because open-collector TTL outputs always sink, never source, current, pullup resistors are necessary when interfacing such an output to a CMOS gate input:

Although the CMOS gates used in the preceding examples were all inverters (single-input), the same principle of pullup and pulldown resistors applies to multiple-input CMOS gates. Of course, a separate pullup or pulldown resistor will be required for each gate input:

This brings us to the next question: how do we design multiple-input CMOS gates such as AND, NAND, OR, and NOR? Not surprisingly, the answer(s) to this question reveal a simplicity of design much like that of the CMOS inverter over its TTL equivalent.

For example, here is the schematic diagram for a CMOS NAND gate:

Notice how transistors Q₁ and Q₃ resemble the series-connected complementary pair from the inverter circuit. Both are controlled by the same input signal (input A), the upper transistor turning off and the lower transistor turning on when the input is "high" (1), and vice versa. Notice also how transistors Q₂ and Q₄ are similarly controlled by the same input signal (input B), and how they will also exhibit the same on/off behavior for the same input logic levels. The upper transistors of both pairs (Q₁ and Q₂) have their source and drain terminals paralleled, while the lower transistors (Q₃ and Q₄) are series-connected. What this means is that the output will go "high" (1) if either top transistor saturates, and will go "low" (0) only if bothlower transistors saturate. The following sequence of illustrations shows the behavior of this NAND gate for all four possibilities of input logic levels (00, 01, 10, and 11):

As with the TTL NAND gate, the CMOS NAND gate circuit may be used as the starting point for the creation of an AND gate. All that needs to be added is another stage of transistors to invert the output signal:

A CMOS NOR gate circuit uses four MOSFETs just like the NAND gate, except that its transistors are differently arranged. Instead of two paralleled sourcing (upper) transistors connected to V_dd and two series-connected sinking (lower) transistors connected to ground, the NOR gate uses two series-connected sourcing transistors and two parallel-connected sinking transistors like this:

As with the NAND gate, transistors Q₁ and Q₃ work as a complementary pair, as do transistors Q₂ and Q₄. Each pair is controlled by a single input signal. If either input A or input B are "high" (1), at least one of the lower transistors (Q₃ or Q₄) will be saturated, thus making the output "low" (0). Only in the event of bothinputs being "low" (0) will both lower transistors be in cutoff mode and both upper transistors be saturated, the conditions necessary for the output to go "high" (1). This behavior, of course, defines the NOR logic function.

The OR function may be built up from the basic NOR gate with the addition of an inverter stage on the output:

Since it appears that any gate possible to construct using TTL technology can be duplicated in CMOS, why do these two "families" of logic design still coexist? The answer is that both TTL and CMOS have their own unique advantages.

First and foremost on the list of comparisons between TTL and CMOS is the issue of power consumption. In this measure of performance, CMOS is the unchallenged victor. Because the complementary P- and N-channel MOSFET pairs of a CMOS gate circuit are (ideally) never conducting at the same time, there is little or no current drawn by the circuit from the V_dd power supply except for what current is necessary to source current to a load. TTL, on the other hand, cannot function without some current drawn at all times, due to the biasing requirements of the bipolar transistors from which it is made.

There is a caveat to this advantage, though. While the power dissipation of a TTL gate remains rather constant regardless of its operating state(s), a CMOS gate dissipates more power as the frequency of its input signal(s) rises. If a CMOS gate is operated in a static (unchanging) condition, it dissipates zero power (ideally). However, CMOS gate circuits draw transient current during every output state switch from "low" to "high" and vice versa. So, the more often a CMOS gate switches modes, the more often it will draw current from the V_dd supply, hence greater power dissipation at greater frequencies.

A CMOS gate also draws much less current from a driving gate output than a TTL gate because MOSFETs are voltage-controlled, not current-controlled, devices. This means that one gate can drive many more CMOS inputs than TTL inputs. The measure of how many gate inputs a single gate output can drive is calledfanout.

Another advantage that CMOS gate designs enjoy over TTL is a much wider allowable range of power supply voltages. Whereas TTL gates are restricted to power supply (V_cc) voltages between 4.75 and 5.25 volts, CMOS gates are typically able to operate on any voltage between 3 and 15 volts! The reason behind this disparity in power supply voltages is the respective bias requirements of MOSFET versus bipolar junction transistors. MOSFETs are controlled exclusively by gate voltage (with respect to substrate), whereas BJTs are current-controlled devices. TTL gate circuit resistances are precisely calculated for proper bias currents assuming a 5 volt regulated power supply. Any significant variations in that power supply voltage will result in the transistor bias currents being incorrect, which then results in unreliable (unpredictable) operation. The only effect that variations in power supply voltage have on a CMOS gate is the voltage definition of a "high" (1) state. For a CMOS gate operating at 15 volts of power supply voltage (V_dd), an input signal must be close to 15 volts in order to be considered "high" (1). The voltage threshold for a "low" (0) signal remains the same: near 0 volts.

One decided disadvantage of CMOS is slow speed, as compared to TTL. The input capacitances of a CMOS gate are much, much greater than that of a comparable TTL gate -- owing to the use of MOSFETs rather than BJTs -- and so a CMOS gate will be slower to respond to a signal transition (low-to-high or vice versa) than a TTL gate, all other factors being equal. The RC time constant formed by circuit resistances and the input capacitance of the gate tend to impede the fast rise- and fall-times of a digital logic level, thereby degrading high-frequency performance.

A strategy for minimizing this inherent disadvantage of CMOS gate circuitry is to "buffer" the output signal with additional transistor stages, to increase the overall voltage gain of the device. This provides a faster-transitioning output voltage (high-to-low or low-to-high) for an input voltage slowly changing from one logic state to another. Consider this example, of an "unbuffered" NOR gate versus a "buffered," or B-series, NOR gate:

In essence, the B-series design enhancement adds two inverters to the output of a simple NOR circuit. This serves no purpose as far as digital logic is concerned, since two cascaded inverters simply cancel:

However, adding these inverter stages to the circuit does serve the purpose of increasing overall voltage gain, making the output more sensitive to changes in input state, working to overcome the inherent slowness caused by CMOS gate input capacitance.